Exam2020Proposed solution included
CEC 217 Computer Architecture Exam 2020
About this paper
CEC 217 Computer Architecture 2019/2020 exam (First semester, Level 200), College of Technology, University of Buea: memory hierarchy.
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University of Buea
College of Technology - COT
Computer Engineering - CET
CEC2172020
Computer Architecture
Exam · First Semester · Level 200
From this paper
- 1.
Which of the following Memory Hierarchy is in a descending order in terms of performance? a) L1, L2, L3, virtual memory, and DRAM b) virtual memory, DRAM L2, L1, L3 c) DRAM, L1, L2, L3 and virtual memory d) L1, L2, L3, DRAM and Virtual Memory
- 4.
Why are DRAMs frequently refreshed? a) Data is read and written b) they are transistors c) Has stronger storage capacity d) they are capacitors
At a glance
- Course code
- CEC217 (CEC 217)
- Type
- Exam
- Year
- 2020
- Level
- Level 200
- Semester
- First Semester
- Proposed solution
- Included
Where it's from
University
University of BueaFaculty
College of Technology - COTDepartment
Computer Engineering - CET
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