CEC 217 Computer Architecture Exam 2021
About this paper
CEC 217 Computer Architecture 2020/2021 exam (First semester, Level 200), College of Technology, University of Buea: I/O transfer, DRAM, clock cycles.
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University of Buea
College of Technology - COT
Computer Engineering - CET
Computer Architecture
Exam · First Semester · Level 200
From this paper
- 4.
Why are DRAMs frequently refreshed? a) Data is read and written b) they are transistors c) Has stronger storage capacity d) they are capacitors
- 8.
Which of the following registers commonly found in the input/output port space of a block transfer device is used to check if the Input / Output transfer is complete? a) Processor status word b) buffer address register c) action register d) status register
At a glance
- Course code
- CEC217 (CEC 217)
- Type
- Exam
- Year
- 2021
- Level
- Level 200
- Semester
- First Semester
- Proposed solution
- Included
Where it's from
University
University of BueaFaculty
College of Technology - COTDepartment
Computer Engineering - CET
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